1. Field of the Invention
The present invention relates to a chip package structure and method of fabricating thereof providing good heat dissipation and absorption of shear stress.
2. Description of Related Art
In consideration of and by requirement of energy conservation and development of new technology for non-polluting energy sources, renewable energy sources have become the focus of attention, especially solar cells. In general, a III-V solar cell chip usually has better photoelectric effect but also has a rather high cost. Therefore, a great area of concentration system is used in association with the III-V solar cell chip to increase the concentration ratio to over a thousand times or more. However, a first problem to be solved for such a system is heat dissipation. In addition, a high power light emitting diode (LED) chip is also one of the current and common concentrator photovoltaic cells but also has the same problem of poor heat dissipation.
During the packaging process, a chip is usually disposed on a substrate and heat conducting adhesive or solder bumps are often used as a bonding medium for the chip and the substrate. The heat conducting adhesive is usually resin having a low coefficient of thermal conductivity and poor heat dissipation. Although the bonding method using solder bumps is easy at fabrication and has a low cost, coefficients of thermal expansion of bonding surfaces differ. Fatigue effect resulted from repetitive changes in temperature during system operation is mainly the reason for damage to bonding points of the chip. Fatigue failure may be classified into mechanical fatigue failure and thermal fatigue failure. Mechanical fatigue failure is due to continuous transformation and movement, resulting in decrease in mechanical strength. Thermal fatigue failure, on the other hand, is caused by poor match of coefficients of thermal expansion between two surfaces, resulting in the two surfaces pulling each other because of minor transformation generated at high and low temperatures, which, under long term influences, may easily cause the surfaces to peel off. As such, the chip and the substrate under the chip are damaged and performance as well as reliability of the chip package structure thereby decreases. In addition, the chip may be bonded to a submount which has a close coefficient of thermal expansion to the coefficient of thermal expansion of the chip. However, a material of the submount is usually ceramic such as Al2O3 and AlN. The structure of high power chip package has to include the submount. Therefore, there exist problems such as a low coefficient of thermal conductivity and high costs.